1. Field of the Invention
The invention relates in general to a design of a mixed mode device, and more particularly to a metal pad positioned on the top of the mixed mode device for connecting to a test device.
2. Description of the Related Art
Conventionally, the most commonly test pattern in a high frequency mixed mode device is a metal-oxide semiconductor transistor with a finger-type polysilicon layer as shown in FIG. 1.
Referring to FIG. 1, a well 102 is formed within a provided substrate 100. A conductive type of the well 102 and a conductive type of the substrate 100 are oppositive. A finger-type polysilicon layer 104 is formed over the substrate 100 and is positioned on the well 102. The finger-type polysilicon layer 104 is used as gates of MOS transistors. Heavily doped regions are formed within the substrate 100 beside the finger-type polysilicon 104. Source/drain regions 106/108 are thus formed. A finger-type first metal layer 110 is formed over the gates. The first metal layer 110 electrically couples with the drain regions 108. A second metal layer 112 with a rectangular shape is formed over the first metal layer 110. The second metal 112 electrically connects to the source regions 106 through vias 114.
A network analyzer is used to test quality of the mixed mode device. The gates of polysilicon 104 are connected to a transmission side of the network analyzer to transfer a current signal. The drain regions 108 of the MOS transistors are connected to a receiver side of the network analyzer to receive the current signal. The source regions 106 and gates of the MOS transistors are grounded.
Since the second metal layer 112 connects to the source regions 106, the source regions 106 are grounded through the second metal layer 112. A circuitry of the mixed mode device is shown in FIG. 2. A voltage is applied on the gate 204 of a MOS transistor. A current is brought from the drain region 202 of the MOS transistor. The mixed mode device shown in FIG. 1 comprises several MOS transistors. Each source region 106 of the MOS transistors is connected to the second metal layer 112 through the vias 114. Areas of the second metal layer 112 over the source regions 106 are the same. Currents of the source regions 106 are the same so that a concourse of the currents to the second metal layer 112 makes a voltage of the second metal layer 112 become higher and higher. A negative feedback is thus formed at the source side.